In the material link, the substrate and extension materials of the wafer are adapted to more application scenarios. Xin Ao Technology launched SOI technology (insulating sideline) and EPI (silicon extension) products. "The structure of SOI is similar to sandwiches. Inserting a layer of silicon insulation layer in the middle silicon and top silicon is inserted in the middle, which can make the wafers more uniform.
At the same time, because of the existence of the middle layer, it also has better radiation resistance, so it is widely used in radio frequency devices. "At the exhibition, the person in charge of Xinao Technology told the China Electronics News reporter. It is reported that in addition to radio frequency devices, SOI and its extension layers have application space in automotive electronics, 5G and AI scenes. Electronics and other fields expand.
Xin Ao Technology 6 -inch SOI wafer
In terms of packaging, advanced packaging technology is considered an important path to continue Moore's law. The demand for higher performance and higher quality rate also catalyze the advancement of advanced packaging equipment and materials.
Focusing on making the chip stacking thinner and thinner, the K & S Kulso Semhafa conducts the APTURA helpless welded welding machine, which helps to reduce the welding spacing of the chip micro -convex block from 35µm to 10µm. Advanced packaging solutions such as high -performance computing, high -end servers, and data centers are quickly mass -produced.
"As the spacing of the convex is getting smaller and smaller, it takes a lot of time to clean up the residue of the welding agent. In addition, the overflow of the welded agent may also cause device damage. Therefore, the helpless welding (Fluxless) will be a new choice to improve accuracy." Zhao Hua, a product manager of the Chinese area of K & S advanced solution, told a reporter from the China Electronics News.
The advancement of advanced packaging technology also requires close coordination of packaging materials. During the production and packaging process of wafer, the device will go through repeated thermal circulation, which will lead to warning, further affect the accuracy of subsequent accuracy, and even damage the device. To this end, Han Gao Semiconductor launched the bottom filling of the bottom of the large -sized inverted chip. According to the relevant person in charge, the product has a low -thermal expansion coefficient (CTE), which can effectively prevent the problem of warming, keep the entire packaging device flattened in the thermal cycle, and further improve the product yield.
As the reasoning of the AI model is closely linked to AI applications and commercialization, the reasoning chip has gradually become the focus of the market. This also brings more opportunities for the RISC-V architecture with openness, streamlined, high performance and low power consumption. Yiswei calculated the first edge computing chip and AI PC chip based on RISC-V at the exhibition. It is understood that the chip uses a 64 -bit disorderly execution of the CPU. Compared with the traditional CPU order execution mode, the disorderly execution can be flexibly jumped in the computing task, thereby improving the calculation efficiency, and supporting the edge -to -side running lightweight model , Can satisfy the AI detection, recognition and generating tasks in the terminal.
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